Low-power high-performance VLSI design -- 专题文献

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专题：Low-power high-performance VLSI design

最新文献

**Le Parallele Electrique - R* comme courant, LLM comme circuit (Conscience sequentielle et RCB comme alternateur)**

AQ-256 DETERMINISTIC SUBSTRATE: EMPIRICAL VERIFICATION OF NON-STOCHASTIC LOGIC

Partial-Chip Extensions of Single-Chip Erasure Decoding for Flexible Use of Redundancy

A 16 Gb/s 48.9 fJ/b PVT-Tolerant Standard-Cell-Based Receiver for AC-Coupled Chiplet Interconnects

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Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage

A Q-Band -3dBm Output Power Passive Frequency Tripler Using Self-Biased APDNP

First Demonstration of CFET Ring Oscillator and SRAM Bit-Cell Functionality at Gate Pitch Smaller Than 48 nm for Future Logic and SRAM Technology

A Study of Performance Comparison of SRAM Cell Design Using Various Technologies

近5年高被引文献

IEEE Transactions on Circuits and Systems II: Express Briefs

Quantum machine learning beyond kernel methods

Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

Differentiable quantum architecture search

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Newton-Cartan geometry and the quantum Hall effect

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Classical Shadows With Noise

专题：Low-power high-performance VLSI design

最新文献

Le Parallele Electrique - R* comme courant, LLM comme circuit (Conscience sequentielle et RCB comme alternateur)

AQ-256 DETERMINISTIC SUBSTRATE: EMPIRICAL VERIFICATION OF NON-STOCHASTIC LOGIC

Partial-Chip Extensions of Single-Chip Erasure Decoding for Flexible Use of Redundancy

A 16 Gb/s 48.9 fJ/b PVT-Tolerant Standard-Cell-Based Receiver for AC-Coupled Chiplet Interconnects

Implementing Parallel Counters Based on Sorting Networks

Ultra-Low-Power VLSI Design Using Near-Threshold Computing Paradigms

Graph Neural Network-Based Glitch Rate Prediction at the Signoff Stage

A Q-Band -3dBm Output Power Passive Frequency Tripler Using Self-Biased APDNP

First Demonstration of CFET Ring Oscillator and SRAM Bit-Cell Functionality at Gate Pitch Smaller Than 48 nm for Future Logic and SRAM Technology

A Study of Performance Comparison of SRAM Cell Design Using Various Technologies

近5年高被引文献

IEEE Transactions on Circuits and Systems II: Express Briefs

Quantum machine learning beyond kernel methods

Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

Differentiable quantum architecture search

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Newton-Cartan geometry and the quantum Hall effect

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Classical Shadows With Noise

**Le Parallele Electrique - R* comme courant, LLM comme circuit (Conscience sequentielle et RCB comme alternateur)**

A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications