专题:Interconnection Networks and Systems

This cluster of papers focuses on the design, architecture, and optimization of Networks on Chip (NoC) within System-on-Chip (SoC) designs. It covers topics such as interconnection networks, routing algorithms, performance evaluation, power optimization, wireless interconnects, fault tolerance, and multi-core processors.
最新文献
The d=6 Exact-Base Branch for E677 Magmas

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Co-Design of Parallel Applications on Heterogeneous Computing Systems Using Reconfigurable Algorithmic Skeletons in OpenCL

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Hierarchical and Distributed Control of AC and DC Microgrid Clusters Interconnected by Flexible DC Distribution Network

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HEC: Heterogeneity-Enriched Communication for AI Symphony

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Topological and Combinatorial Invariants of Trajectory Spaces on Hypercubes

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Dynamic response characteristics and failure prediction of cylindrical lithium-ion batteries under low-velocity impact

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Design and Verification of Gray Coded FSM based 3D NoC Router using Verilog HDL

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A Strong Structural Stability of C2k+1‐Free Graphs

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On Solving the Shortest Paths with Exclusive-Disjunction Arc Pairs Conflicts

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Triangle graph connectivity as a necessary condition for spectral lower bounds: obstructions, a strong empirical conjecture, and the limits of local triangle support

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近5年高被引文献
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings

article Full Text OpenAlex 408 FWCI180.077

IEEE Standard for Interconnection and Interoperability of Inverter-Based Resources (IBRs) Interconnecting with Associated Transmission Electric Power Systems

standard Full Text OpenAlex 292 FWCI0

A survey on data plane programming with P4: Fundamentals, advances, and applied research

article Full Text OpenAlex 185 FWCI23.5334

Jupiter evolving

article Full Text OpenAlex 182 FWCI24.4033

Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

article Full Text OpenAlex 165 FWCI14.3137

A new adaptive selection strategy for reducing latency in networks on chip

article Full Text OpenAlex 138 FWCI19.1181

Hierarchical Domain-Based Multicontroller Deployment Strategy in SDN-Enabled Space–Air–Ground Integrated Network

article Full Text OpenAlex 127 FWCI79.0439

RISC-V Instruction Set Architecture Extensions: A Survey

article Full Text OpenAlex 106 FWCI31.4938

High-Quality Hypergraph Partitioning

article Full Text OpenAlex 100 FWCI8.3131

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

article Full Text OpenAlex 94 FWCI18.6742