专题：Advancements in PLL and VCO Technologies

This cluster of papers focuses on the design, analysis, and optimization of phase-locked loops (PLLs) and related components in high-speed circuits. Topics include frequency synthesizers, time-to-digital converters, jitter analysis, digital PLLs, charge pumps, clock recovery techniques, delta-sigma modulators, and their application in high-speed communication systems.
最新文献
A Low-Cost Open-Loop Fractional Output Divider for Audio System-on-Chip in 180 nm CMOS

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Capse.jl: efficient and auto-differentiable CMB power spectra emulation

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When Barkhausen's Criterion Does Not Suffice and you Must Rely on the Forgotten Art of Oscillator Design

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Practical deployment of subsampling-based high-frequency signal acquisition system

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EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design

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Design and Performance Analysis of a Low Jitter Charge Pump-Phase Locked Loop Architecture and Loop Filter in CMOS Process

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A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

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The Design of the CIC-HB Digital Decimation Filter for the Sigma-Delta Modulator

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A full-scale complementary dynamic comparator

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Frequency source design of solid-state microwave source based on phase-locked loop technology

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近5年高被引文献
Analog-to-Digital Conversion

book Full Text OpenAlex 137 FWCI7.69557697

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

article Full Text OpenAlex 109 FWCI6.87610672

Jitter-Power Trade-Offs in PLLs

article Full Text OpenAlex 81 FWCI5.86761107

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation

article Full Text OpenAlex 76 FWCI28.05838988

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

article Full Text OpenAlex 72 FWCI5.77592965

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2

article Full Text OpenAlex 66 FWCI4.85911542

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET

article Full Text OpenAlex 65 FWCI4.21734546

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW

article Full Text OpenAlex 60 FWCI4.25050567

Time-to-Digital Converter IP-Core for FPGA at State of the Art

article Full Text OpenAlex 60 FWCI15.82830372

IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired–Wireless TSN Architecture

article Full Text OpenAlex 56 FWCI7.78469252