专题：Advancements in PLL and VCO Technologies

This cluster of papers focuses on the design, analysis, and optimization of phase-locked loops (PLLs) and related components in high-speed circuits. Topics include frequency synthesizers, time-to-digital converters, jitter analysis, digital PLLs, charge pumps, clock recovery techniques, delta-sigma modulators, and their application in high-speed communication systems.
最新文献
Interconnect Simulation Using Padé Approximation for Image Sensors

article Full Text OpenAlex

A 16~21GHz 5-Bit High-Accuracy Attenuator

article Full Text OpenAlex

Design and Performance of an Ultra-Low Power Wake-Up Timer for N-FET Based FlexIC Technologies

article Full Text OpenAlex

Design of BPC LF Time Code Signal Generator Based on ARM Architecture Microcontroller and FPGA

article Full Text OpenAlex

A 6-bit CMOS Attenuator With Low Phase Variation Using a Bandpass Response Capacitive π-Bridge Network

article Full Text OpenAlex

A Low-EMI Fast-Transient-Response Buck Converter Using Delta-Sigma Modulation

article Full Text OpenAlex

Phase-Locked Loop Design for 32Gbps/s High-Speed Serial Interface

article Full Text OpenAlex

A Novel Tunable Low-Noise Active Inductor

article Full Text OpenAlex

Beethoven: A Heterogeneous Multi-Core Accelerator System Composer

article Full Text OpenAlex

Deduction of Oscillation Amplitudes using SCADA

article Full Text OpenAlex

近5年高被引文献
Analog-to-Digital Conversion

book Full Text OpenAlex 136 FWCI5.287

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

article Full Text OpenAlex 66 FWCI4.486

Jitter-Power Trade-Offs in PLLs

article Full Text OpenAlex 59 FWCI4.486

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

article Full Text OpenAlex 59 FWCI19.869

Time-to-Digital Converter IP-Core for FPGA at State of the Art

article Full Text OpenAlex 56 FWCI11.116

IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired–Wireless TSN Architecture

article Full Text OpenAlex 47 FWCI5.682

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation

article Full Text OpenAlex 47 FWCI22.71

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW

article Full Text OpenAlex 46 FWCI3.422

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2

article Full Text OpenAlex 43 FWCI3.365

A SModelS interface for pyhf likelihoods

article Full Text OpenAlex 43 FWCI9.044